A non-volatile memory cell, a widely used semiconductor device, is capable to preserve digital information without supply of electric power. An erasable programmable ROM (EPROM), one of the non-volatile memory cells fabricated based on a semiconductor substrate, preserves digital information by trapping electrons in its floating gate when some electrodes of the EPROM are biased in desired levels. The electrons trapped in the floating gate of the EPROM could be evacuated to erase the preserved information by exposing the EPROM in an environment with a high dose of ultraviolet. Since the EPROM has the feature of repeatedly recording information in a state out of supply of electric power, today it is employed in many electronic devices.
Referring to FIG. 1, an EPROM cell is fabricated on a silicon substrate 102 doped with P-type impurities, such as B, BF.sub.2.sup.+. A silicon dioxide layer 108 formed on the surface of the P-substrate 102 encompasses a floating gate 110 and control gate 112, in which the two gates are insulated by the silicon dioxide layer 108. A source region 104 and drain region 106 doped with N-type impurities, such as P or As, are embedded at opposite two sides of the floating gate 110 in the P-type substrate 102. When recording information in the EPROM cell, the control gate 112 and drain region 106 are biased in a high voltage level, meanwhile the source region 104 and substrate 102 are electrically connected to ground, to drive electrons being ejected from the source region 104 through the silicon dioxide layer 108 into the floating gate 110. The silicon dioxide layer 108 would construct a potential barrier so as to trap the electrons in the floating gate 110. Because of the electrons trapped in the floating gate, when the control gate 112 is biased to its original threshold voltage level, the channel between the source region 104 and drain region 106 will not normally be turned on, therefore regarding this state as "1". Contrarily, if the EPROM cell is not biased to eject electrons into the floating gate 110, the channel between the source region 104 and drain region 106 will be turned on, as long as the control gate 112 is biased to its threshold voltage level. Such a state would be regarded as "0".
To erase the preserved information, the EPROM needs tobe exposed to an ultraviolet environment for providing the trapped electrons with enough energy to escape from the potential barrier of the silicon dioxide layer 108. By applying the erasing and recording procedures, the EPROM cell can be repeatedly performed to preserve digital information.
Commonly, the EPROM cell includes two stacked gates, the control gate 112, and floating gate 110. To approach the two gates, a more complicated fabricating process is needed to form the two-layer structure. For forming an EPROM chip, EPROM cells are always designed in association with logic devices, such as MOSFET, CMOSFET, and so on. However, the MOSFET and CMOSFET are both one-layer structures with fewer lithographic masks than those of the EPROM cells, so as to make the fabricating processes of the EPROM cell being somewhat incompatible from that of the MOSFET and CMOSFET. For fitting the fabricating processes of the EPROM cell, the processes of the EPROM chip would become costly and complicated.
The traditional EPROM cell could provide a high integration, but in some cases the EPROM chip does not need such a high integration but the concren is more about the cost and simplicity of fabricating processes. Under this concern, the present invention demonstrates a single poly non-volatile memory structure and its fabricating method for improving the disadvantages which exist in the prior art.